CAS=RESERVED, RAS=RESERVED
Selects the RAS and CAS latencies for dynamic memory chip select 0.
| RAS | RAS latency (active to read/write delay). 0 (RESERVED): Reserved. 1 (ONE_EMC_CCLK_CYCLE): One EMC_CCLK cycle. 2 (TWO_EMC_CCLK_CYCLES): Two EMC_CCLK cycles. 3 (THREE_EMC_CCLK_CYCLE): Three EMC_CCLK cycles (POR reset value). |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |
| CAS | CAS latency. 0 (RESERVED): Reserved. 1 (ONE_EMC_CCLK_CYCLE): One EMC_CCLK cycle. 2 (TWO_EMC_CCLK_CYCLES): Two EMC_CCLK cycles. 3 (THREE_EMC_CCLK_CYCLE): Three EMC_CCLK cycles (POR reset value). |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |